Effect of Top-Gate Dielectric Deposition on the Performance of Indium Tin Oxide Transistors
Sumaiya Wahid, Alwin Daus, Jimin Kwon, Shengjun Qin, Jung-Soo Ko, H.‐S. Philip Wong, Eric Pop
Abstract
We report ultrathin ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\sim }4$ </tex-math></inline-formula> nm) channel indium tin oxide (ITO) transistors, comparing different precursors for atomic layer deposition (ALD) of the Al2O3 top-gate dielectric, and analyze the role of dielectric deposition on transistor performance and gate bias stress stability. Water-based ALD leads to very negative threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula> ), with devices remaining in the on-state. In contrast, both ozone and O2-plasma precursors yield devices that can turn off, but ozone-based ALD devices have less negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula> shift at short channel lengths, and relatively more positive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula> at all channel lengths. We achieve maximum drive current, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {max}} \approx 260 \mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}=$ </tex-math></inline-formula> 1 V, on/off current ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{10}}$ </tex-math></inline-formula> (limited by the instrument’s noise floor) for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L} \approx 700$ </tex-math></inline-formula> nm ozone-Al2O3 top-gated transistors. Across multiple devices, the effective mobility is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 42 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ </tex-math></inline-formula> and contact resistance is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 376 \Omega \cdot \mu \text{m}$ </tex-math></inline-formula> . The transistors also show good gate bias stability with normalized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula> shift of +0.12 V(MV/cm) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{1}}$ </tex-math></inline-formula> at gate stress field >3 MV/cm, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 3\times $ </tex-math></inline-formula> improvement vs. our previous reports of uncapped ITO transistors.