Highly Robust All-Oxide Transistors Toward Vertical Logic and Memory
Zehao Lin, Zhuocheng Zhang, Chang Niu, Hongyi Dou, Ke Xu, Mir Md Fahimul Islam, Jian-Yu Lin, Changhyuck Sung, Minji Hong, Daewon Ha, Haiyan Wang, Muhammad Ashraful Alam, Peide D. Ye
Abstract
In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In2O3 as the conducting gate, and ALD In2O3 thin film itself serves as source/drain contacts to the ALD In2O3 channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400~^{\circ }$ </tex-math></inline-formula> C but also gained a boosted on-/off-ratio over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{7}}$ </tex-math></inline-formula> with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta } {V}_{\text {TH}}\text {)}$ </tex-math></inline-formula> of −5 and −50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$ </tex-math></inline-formula> s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In2O3 with thickness as well as gate length (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {IO,{g}}}\text {)}$ </tex-math></inline-formula> of 10 nm, achieving on-/off-ratio over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{5}}$ </tex-math></inline-formula> and maximum current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\max }\text {)}$ </tex-math></inline-formula> over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$160~\boldsymbol {\mu } $ </tex-math></inline-formula> A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\mu } $ </tex-math></inline-formula> m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{12}}$ </tex-math></inline-formula> cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.