Investigation of tied double gate 4H–SiC junctionless FET in 7 nm channel length with a symmetrical dual p+ layer
Dariush Madadi, Ali A. Orouji
Topics & Concepts
Materials scienceDrain-induced barrier loweringOptoelectronicsThreshold voltageDouble gateCurrent (fluid)TransistorVoltageIonWork functionField-effect transistorDual (grammatical number)Channel (broadcasting)Layer (electronics)Gate voltageElectrical engineeringNanotechnologyMOSFETPhysicsArtQuantum mechanicsLiteratureEngineeringSilicon Carbide Semiconductor TechnologiesAdvancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devices