SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators
H C Prashanth, Madhav Rao
Abstract
Approximate computing along with quantized low-precision computing has gained significant interest in today’s neural network (NN) implementation. This paper proposes a library of VLSI implementations of different activation functions, aimed towards designing hardware-efficient NN accelerators. Cartesian genetic programming (CGP), an evolutionary algorithm was employed to generate gate-level designs of approximate and exact representations of activation functions. We open-source the hardware library of 9444 circuits containing a majority of the activation functions employed in NN architectures, including Sigmoid, Hyperbolic-Tangent, Gaussian, ReLU, GeLU, Softplus, and Binary-Step. The library also presents the error characteristics and hardware metrics of the designs which will aid in the usage of the library in future research. Additionally a hardware comparison of the proposed circuits against existing implementations including piecewise-linear (PWL), memory-based, hls4ml, DNNweaver implementations to realize activation functions on FPGA and ASIC flow is presented. The CGP evolved hardware library shows minimal silicon space requirement, least power consumption when investigated for ASIC flow, and the least LUT utilization’s in FPGA flow. Besides, SOMALib designs are purely combinatorial, allowing various synthesis stage optimizations towards the target Power-Performance-Area budget, which is not possible in standard memory block implementations.