High-performance and low parasitic capacitance CNT MOSFET: 1.2 mA/μm at V<sub>DS</sub> of 0.75 V by self-aligned doping in sub-20 nm spacer
Shengman Li, Tzu‐Ang Chao, Carlo Gilardi, Nathaniel S. Safron, Sheng‐Kai Su, Gilad Zeevi, Andrew Denis Bechdolt, M. Passlack, Aaryan Oberoi, Qing Lin, Ziehen Zhang, Kesong Wang, Harshil Kashyap, San‐Lin Liew, Vincent Hou, Andrew C. Kummel, Luliana Radu, Gregory Pitner, H.‐S. Philip Wong, Subhasish Mitra
Abstract
For the first time we report degenerate and self-aligned doping in the sub-20nm spacer region on a high-density CNT channel to achieve high-performance CNT p-MOSFET with I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> = 12 mA/μm at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> = -0.75 V, CGP = 160 nm, and L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> = 50 nm. The extension doping lowers the effective energy barrier height near the contact from 228 meV to 50 meV. The parasitic resistance remains 250 Ω•μm for contact lengths ranging from 100 nm to 20 nm. Calculated intrinsic gate delay (τ=RC=CV/I, including gate and spacer capacitances) based on resistance and spacer capacitance values of experimental structures, indicate that the doped-spacer MOSFET enables intrinsic gate delay ~2× lower vs. SBFET and ~2.6× lower vs. undoped-spacer MOSFET. These benefits are even more significant for shorter channel lengths. Strategies for overcoming channel quality and gate interface non-idealities are discussed.