An Enhancement-Mode GaN p-FET With Improved Breakdown Voltage
Hao Jin, Qimeng Jiang, Sen Huang, Xinhua Wang, Yingjie Wang, Zhongchen Ji, Xinyue Dai, Chao Feng, Jie Fan, Wei Ke, Jianxun Liu, Yaozong Zhong, Qian Sun, Xinyu Liu
Abstract
In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistors (p-FETs) with current density of −5.6 mA/mm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{{\mathrm {ON}}}/{I} _{{\mathrm {OFF}}}$ </tex-math></inline-formula> ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> was demonstrated on a p-GaN/AlN/AlGaN/GaN heterostructure on Si substrate. A decent ohmic contact resistivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.25 \times 10^{-5} \Omega \cdot {\mathrm {cm}}^{2}$ </tex-math></inline-formula> is achieved by capping the heterostructure with a 10-nm heavily Mg-doped p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> -GaN epilayer. A two-step gate trench etching process, is implemented to overcome the decreased OFF-state blocking voltage associated with the surface p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> -GaN layer. The proposed structure is compelling for monolithic integration of GaN-based logic and power devices.