Spacer Design Strategies at Sub-5-nm Technology Node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy—A Dielectric Perspective
Devika Gurre, Vinai Dasari, Kavya Mulaga, Sresta Valasa, Venkata Ramakrishna Kotha, Sunitha Bhukya, Praveen Kumar Mudidhe, Shubham Tayal, Bheemudu Vadthya, Narendar Vadthiya
Abstract
For the first time, this work presents the spacer design guidelines for the Junctionless Forksheet FET (JL-FSFET) at the sub-5-nm technology node. Recently, this device emerged as the futuristic candidate owing to the integration of nFET and pFET with minimal n-p spacing. With a fixed gate length (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {g}}$ </tex-math></inline-formula>) of 16 nm, we explore the influence of various spacer materials (Air, SiO2, Si3 N4, HfO2, and TiO2) on digital, analog/radio frequency (RF), and circuit performance metrics. The suitable spacer design materials (single-k and dual-k) are evaluated to identify optimal material combinations that enhance device efficiency and performance. Among single-k spacers, TiO2 emerges as the best suitable material for digital and analog applications with SS ~62.6 mV/dec and a switching ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10^{{10}}$ </tex-math></inline-formula>. In contrast, the Air spacer proves as a better material for RF applications owing to the reduction in parasitic capacitances. To enhance device performance further, we explore four dual-k spacer (inner high-k + outer low-k) configurations: HfO<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{2}} + $ </tex-math></inline-formula> Air, HfO<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{2}} + $ </tex-math></inline-formula> SiO2, TiO<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{2}} + $ </tex-math></inline-formula> Air, and TiO<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{2}} + $ </tex-math></inline-formula> SiO2. Results indicate that Air + inner high-k materials are suitable for optimal RF performance whereas for digital performance, SiO<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{{2}} + $ </tex-math></inline-formula> TiO2 combination is preferable with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 5\times $ </tex-math></inline-formula> improvement in switching ratio. Additionally, a better digital and analog performance is obtained by increasing the inner high-k spacer length, though it considerably reduces the RF performance. Moreover, the JL-FSFET-based CMOS inverter achieves gain (delay) of approximately ~10 V/V (~6.1 ps) making it quite desirable to adopt into advanced digital IC applications. Overall, this work provides the design strategies for the device engineers to optimize the spacer design guidelines to adopt in futuristic digital, analog/RF applications.