Reliability Assessment of Double-Gated Wafer-Scale MoS<sub>2</sub> Field Effect Transistors through Hysteresis and Bias Temperature Instability Analyses
Alexandros Provias, Theresia Knobloch, A. Kitamura, K. P. O’Brien, C. J. Dorow, Dominic Waldhoer, Bernhard Stampfer, Ashish Verma Penumatcha, S. Lee, R. Ramamurthy, Scott B. Clendenning, Michael Waltl, Uygar E. Avci, Tibor Grasser
Abstract
2D field-effect transistors (FETs) based on transition metal dichalcogenides (TMDs) are a potential replacement for silicon transistors at sub-12 nm channel lengths (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> ). Here, we demonstrate initial reliability and performance for double-gated NMOS FETs based on molybdenum disulfide (MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ) as a channel material with a HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> back gate and a Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> /HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> top gate stack fabricated in an industry lab. We present a comprehensive analysis of hysteresis curves obtained at varying sweep rates of the top gate bias (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TG</inf> ) for varying temperatures (T), and static back gate biasing conditions (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BG</inf> ) as well as bias temperature instability (BTI) measurements. Our primary objective is to assess the impact of charge trapping from the channel and the gate side as well as ion diffusion on the observed degradation behavior. Our analysis reveals excellent stability in terms of hysteresis as well as good behaviour in terms of BTI relative to published 2D FETs, even though it is still higher than in commercial Si/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> stacks.